This automotive AEC-Q100 qualified singlepositive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferredto the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltagelevel and is not directly related to the rise time of the clock pulse. Following the hold-timeinterval, data at the D input can be changed without affecting the level at the output.
This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
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| Status | ACTIVE |
| SubFamily | D-type flip-flop |
| Technology Family | LVC |
| VCC | 5.5 |
| Bits | 1 |
| Voltage | 3.3 |
| F @ nom voltage | 150 |
| ICC @ nom voltage | 0.01 |
| tpd @ Nom Voltage | 12^8.5^6^5 |
| 3-state output | No |
| Rating | Automotive |
| Operating temperature range | -40 to 125 |
| Package Group | SC70|5 |
| Package size: mm2:W x L (PKG) | [pf]5SC70[/pf]: 4 mm2: 2.1 x 2 (SC70|5) |
| Approx. price | 0.08 | 1ku |