SN74LS107A - Dual J-K Flip-Flops With Clear

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.

 

Products containing the "SN74LS107A" keyword are: SN74LS107AD , SN74LS107AD , SN74LS107ADBR , SN74LS107ADG4 , SN74LS107ADG4 , SN74LS107ADR , SN74LS107ADR , SN74LS107ADRE4 , SN74LS107ADRE4 , SN74LS107ADRG4 , SN74LS107ADRG4 , SN74LS107AJ , SN74LS107AN , SN74LS107AN , SN74LS107AN/MB74LS107 , SN74LS107ANE4 , SN74LS107ANS , SN74LS107ANSE4 , SN74LS107ANSR , SN74LS107ANSR

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