SN74AUC1G79 - Single Positive-Edge-Triggered D-Type Flip-Flop

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-VV_CC, but is designed specifically for 1.65-V to 1.95-VV_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferredto the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltagelevel and is not directly related to the rise time of the clock pulse. Following the hold-timeinterval, data at the D input can be changed without affecting the levels at the outputs.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.

This device is fully specified for partial-power-down applications usingI_off. The I_off circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Available in the Texas Instruments NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• I_off Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max t_pd of 1.9 ns at 1.8 V
• Low Power Consumption, 10-µA Maximum I_CC
• ±8-mA Output Drive at 1.8 V

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