These positive-edge-triggered D-type flip-flops have a direct clear (CLR)\ input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
Products containing the "SN54HC174" keyword are: SN54HC174JStatus | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | HC |
VCC | 6 |
Bits | 6 |
Voltage | 3.3^5 |
F @ nom voltage | 28 |
ICC @ nom voltage | 0.08 |
tpd @ Nom Voltage | 34 |
3-state output | No |
Rating | Military |
Operating temperature range | -55 to 125 |
Package Group | CDIP|16 |
Package size: mm2:W x L (PKG) | See datasheet (CDIP) |
Approx. price |