These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the ACT374 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.
OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Status | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | ACT |
VCC | 5.5 |
Bits | 8 |
Voltage | 5 |
F @ nom voltage | 90 |
ICC @ nom voltage | 0.04 |
tpd @ Nom Voltage | 11.5 |
3-state output | Yes |
Rating | Military |
Operating temperature range | -55 to 125 |
Package Group | CDIP|20 |
Package size: mm2:W x L (PKG) | See datasheet (CDIP) |
Approx. price |