These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs, regardless of the levels of the other inputs. When
and
are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C.
Products containing the "SN54ALS112A" keyword are: SN54ALS112AJ
| Status | ACTIVE |
| SubFamily | J-K flip-flop |
| Technology Family | ALS |
| VCC | 5.5 |
| Bits | 2 |
| Voltage | 5 |
| F @ nom voltage | 75 |
| ICC @ nom voltage | 4.5 |
| tpd @ Nom Voltage | 18 |
| 3-state output | No |
| Rating | Military |
| Operating temperature range | -55 to 125 |
| Package Group | CDIP|16 |
| Package size: mm2:W x L (PKG) | See datasheet (CDIP) |
| Approx. price |