CD74HCT109 - High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset

The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).

The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.

Products containing the "CD74HCT109" keyword are: CD74HCT109E , CD74HCT109E , CD74HCT109EE4 , CD74HCT109EG4 , CD74HCT109EX , CD74HCT109M , CD74HCT109M , CD74HCT109M96 , CD74HCT109M96 , CD74HCT109M96E4 , CD74HCT109M96G4 , CD74HCT109ME4 , CD74HCT109MG4 , CD74HCT109MG4 , CD74HCT109MT , CD74HCT109MT , CD74HCT109MTE4 , CD74HCT109MTG4

• Asynchronous Set and Reset
• Schmitt Trigger Clock Inputs
• Typical f_MAX = 54MHz at V_CC = 5V, C_L = 15pF, A = 25°C
• Fanout (Over Temperature Range)
  • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
  • CMOS Input Compatibility, I_l 1µA at V_OL, V_OH