CD74HC194 - High Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register

The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin.

Products containing the "CD74HC194" keyword are: CD74HC1940PW , CD74HC194E , CD74HC194E , CD74HC194EE4 , CD74HC194M , CD74HC194M , CD74HC194M96 , CD74HC194M96 , CD74HC194M96E4 , CD74HC194M96G4 , CD74HC194ME4 , CD74HC194MG4 , CD74HC194MT , CD74HC194MT , CD74HC194MTE4 , CD74HC194NSR , CD74HC194NSR , CD74HC194NSRE4 , CD74HC194NSRE4 , CD74HC194NSRG4

• Four Operating Modes
  • Shift Right, Shift Left, Hold and Reset
• Synchronous Parallel or Serial Operation
• Typical f_MAX = 60MHz at V_CC = 5V, C_L = 15pF, T_A = 25°C
• Asynchronous Master Reset
• Fanout (Over Temperature Range)
  • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
  • CMOS Input Compatibility, I_l 1µA at V_OL, V_OH