CD74HC112 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Set, Reset, and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs.

The HCT logic family is functionally as well as pin-compatible with the standard LS logic family.

Products containing the "CD74HC112" keyword are: CD74HC112E , CD74HC112EE4 , CD74HC112M , CD74HC112M96 , CD74HC112M96 , CD74HC112M96E4 , CD74HC112M96G4 , CD74HC112MT , CD74HC112MT , CD74HC112MTE4 , CD74HC112MTG4 , CD74HC112NSR , CD74HC112NSR , CD74HC112NSRE4 , CD74HC112NSRG4 , CD74HC112PW , CD74HC112PW , CD74HC112PWE4 , CD74HC112PWG4 , CD74HC112PWR

• Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
• Asynchronous Set and Reset
• Complementary Outputs
• Buffered Inputs
• Typical f_MAX = 60MHz at V_CC = 5V, C_L = 15pF, T_A = 25°C
• Fanout (Over Temperature Range)
  • Standard Outputs . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
  • CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor