CD54HCT259 - High Speed CMOS Logic 8-Bit Addressable Latch

The ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky.

This latches three active modes and one reset mode. When both the Latch Enable (LE\) and Master Reset (MR\) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR\ and LE\ are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE\ transition from low to high. A condition of LE\ low and MR\ high (Addressable Latch mode) allows the addressed latch’s output to follow the data input; all other latches are unaffected. The Reset mode (all outputs low) results when LE\ is high and MR\ is low.

Products containing the "CD54HCT259" keyword are: CD54HCT259F , CD54HCT259F .. , CD54HCT259F3A , CD54HCT259F3A 5962-89852

• Buffered Inputs and Outputs
• Four Operating Modes
• Typical Propagation Delay of 15ns at V_CC = 5V, C_L = 15pF, T_A = 25°C
• Fanout (Over Temperature Range)
  - Standard Outputs...10 LSTTL Loads
  - Bus Driver Outputs...15 LSTTL Loads
• Wide Operating Temperature Range... –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  - 2V to 6V Operation
  - High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
  - 4.5V to 5.5V Operation
  - Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
  - CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor