SN74LV125AT - Quadruple Bus Buffer Gate With 3-State Outputs

The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74LV125AT" keyword are: SN74LV125ATD , SN74LV125ATD , SN74LV125ATDB , SN74LV125ATDBE4 , SN74LV125ATDBE4 , SN74LV125ATDBG4 , SN74LV125ATDBR , SN74LV125ATDG4 , SN74LV125ATDR , SN74LV125ATDR , SN74LV125ATNS , SN74LV125ATNSG4 , SN74LV125ATNSG4 , SN74LV125ATNSR , SN74LV125ATNSR , SN74LV125ATNSRG4 , SN74LV125ATPW , SN74LV125ATPWE4 , SN74LV125ATPWE4 , SN74LV125ATPWR

• Inputs Are TTL-Voltage Compatible
• 4.5-V to 5.5-V V_CC Operation
• Typical t_pd of 3.8 ns at 5 V
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 5 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
  >2.3 V at V_CC = 5 V, T_A = 25°C
• Support Mixed-Mode Voltage Operation on All Ports
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)