SN74AVC16244 - 16-Bit Buffer/Driver With 3-State Outputs

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V_OL vs I_OL and V_OH vs I_OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC^TM) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit buffer/driver is operational at 1.2-V to 3.6-V V_CC, but is designed specifically for 1.65-V to 3.6-V V_CC operation.

The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE\) inputs.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Products containing the "SN74AVC16244" keyword are: SN74AVC16244DGGR , SN74AVC16244DGGR , SN74AVC16244DGGR/BKN , SN74AVC16244DGGRG4 , SN74AVC16244DGVR , SN74AVC16244DGVR , SN74AVC16244DGVRG4 , SN74AVC16244GQLR , SN74AVC16244GQLR , SN74AVC16244ZQLR , SN74AVC16244ZQLR

• Member of the Texas Instruments Widebus™ Family
• DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
• Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V V_CC
• Dynamic Drive Capability Is Equivalent to Standard Outputs With I_OH and I_OL of ±24 mA at 2.5-V V_CC
• Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)

DOC and Widebus are trademarks of Texas Instruments.