CD4502B - CMOS Strobed Hex Inverter/Buffer with 3-State Outputs

CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series I_OL standard.

The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD4502B" keyword are: CD4502B , CD4502BD , CD4502BD/3 , CD4502BE , CD4502BE , CD4502BEE4 , CD4502BEE4 , CD4502BEG4 , CD4502BEX , CD4502BF , CD4502BF/3 , CD4502BF3A , CD4502BF3A 7702002EA , CD4502BF3A(CD4502BF) , CD4502BFX , CD4502BM , CD4502BM , CD4502BM96 , CD4502BM96 , CD4502BM96 12+

• 2 TTL-load output drive capability
• 3-state outputs
• Common output-disable control
• Inhibit control
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
• Noise Margin (full package-temperature range) =
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
• Applications:
  • 3-state hex inverter for interfacing IC's with data buses
  • COS/MOS to TTL hex buffer