SN74LV08A - Quadruple 2-Input Positive-AND Gates

Updated : 2020-01-09 14:38:35

Description

This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V V_CC operation. The SN74LV08A device performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.

Products containing the "SN74LV08A" keyword are: SN74LV08AD , SN74LV08AD , SN74LV08AD/LV08A , SN74LV08ADBR , SN74LV08ADBR , SN74LV08ADE4 , SN74LV08ADE4 , SN74LV08ADG4 , SN74LV08ADG4 , SN74LV08ADGV , SN74LV08ADGVR , SN74LV08ADGVR , SN74LV08ADGVRE4 , SN74LV08ADGVRG4 , SN74LV08ADGVRG4 TVSOP14 , SN74LV08ADR , SN74LV08ADR , SN74LV08ADRE4 , SN74LV08ADRE4 , SN74LV08ADRG4

Features

2-V to 5.5-V V_CC Operation
Max t_pd of 7 ns at 5 V
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2.3 V at V_CC = 3.3 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
I_off Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model
- 200-V Machine Model
- 1000-V Charged-Device Model

Parametrics

Status	ACTIVE
SubFamily	AND gate
Technology Family	LV-A
VCC	5.5
Channels	4
Inputs per channel	2
ICC @ nom voltage	0.02
IOL	12
IOH	-12
Input type	Standard CMOS
Output type	Push-Pull
Features	Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Very High Speed (tpd 5-10ns)
Data rate	70
Rating	Catalog
Operating temperature range	-40 to 125
Package Group	SOIC\|14
Package size: mm2:W x L (PKG)	[pf]14SO[/pf]: 80 mm2: 7.8 x 10.2 (SO\|14)
Approx. price	0.07 \| 1ku