SN74AUC2G00 - DUAL 2-INPUT POSITIVE-NAND GATE

This dual 2-input positive-NAND gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC2G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74AUC2G00" keyword are: SN74AUC2G00DCT , SN74AUC2G00DCTR , SN74AUC2G00DCTR , SN74AUC2G00DCTRE4 , SN74AUC2G00DCTRE4 , SN74AUC2G00DCUR , SN74AUC2G00DCUR , SN74AUC2G00DCURE4 , SN74AUC2G00DCURG4 , SN74AUC2G00DCURG4 , SN74AUC2G00YEPR , SN74AUC2G00YZPR , SN74AUC2G00YZPR , SN74AUC2G00YZPRB , SN74AUC2G00YZTR

• Available in the Texas Instruments NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• I_off Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max t_pd of 1.2 ns at 1.8 V
• Low Power Consumption, 10 µA at 1.8 V
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

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