This quadruple 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC00 devices perform the Boolean function Y = A B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Products containing the "SN74AUC00" keyword are: SN74AUC00RGYR , SN74AUC00RGYR , SN74AUC00RGYRG4 , SN74AUC00RGYRG4Status | ACTIVE |
SubFamily | NAND gate |
Technology Family | AUC |
VCC | 2.7 |
Channels | 4 |
Inputs per channel | 2 |
ICC @ nom voltage | 0.01 |
IOL | 8 |
IOH | -8 |
Input type | Standard CMOS |
Output type | Push-Pull |
Features | Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Ultra High Speed (tpd <5ns) |
Data rate | 250 |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | VQFN|14 |
Package size: mm2:W x L (PKG) | [pf]14VQFN[/pf]: 12 mm2: 3.5 x 3.5 (VQFN|14) |
Approx. price | 0.26 | 1ku |