The TLC220x, TLC220xA, TLC220xB, and TLC220xY are precision, low-noise operational amplifiers using Texas Instruments Advanced LinCMOS process. These devices combine the noise performance of the lowest-noise JFET amplifiers with the dc precision available previously only in bipolar amplifiers. The Advanced LinCMOS process uses silicon-gate technology to obtain input offset voltage stability with temperature and time that far exceeds that obtainable using metal-gate technology. In addition, this technology makes possible input impedance levels that meet or exceed levels offered by top-gate JFET and expensive dielectric-isolated devices.
The combination of excellent DC and noise performance with a common-mode input voltage range that includes the negative rail makes these devices an ideal choice for high-impedance, low-level signal-conditioning applications in either single-supply or split-supply configurations.
The device inputs and outputs are designed to withstand 100-mA surge currents without sustaining latch-up. In addition, internal ESD-protection circuits prevent functional failures at voltages up to 2000 V as tested under MIL-PRF-38535, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in degradation of the parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from 40°C to 85°C. The M-suffix devices are characterized for operation over the full military temperature range of 55°C to 125°C.
Products containing the "TLC2201M" keyword are: TLC2201MFKB , TLC2201MLBAdvanced LinCMOS is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
Status | ACTIVE |
Number of channels | 1 |
Total Supply Voltage | 4.6 |
Vos (offset voltage @ 25 C) | 0.5 |
GBW | 1.8 |
Slew Rate | 2.5 |
Rail-to-rail | In to V-^Out |
Offset drift | 0.5 |
Iq per channel | 1 |
Vn at 1 kHz | 8 |
CMRR | 110 |
Rating | Military |
Operating temperature range | -55 to 125 |
Package Group | CDIP|8 |
Approx. price | |
Package size: mm2:W x L (PKG) | See datasheet (CDIP) |
Input bias current | 60 |
Output current | 4.5 |
Features | N/A |
Architecture | CMOS |
Input common mode headroom (to negative supply) | 0.0 |
Input common mode headroom (to positive supply) | -2.3 |
Output swing headroom (to negative supply) | 0.05 |
Output swing headroom (to positive supply) | -0.2 |