SN74AXC1T45 - Single-Bit Dual-Supply Bus Transceiver

The SN74AXC1T45 is a single-bit noninverting bustransceiver that uses two separate configurable power-supply rails. The device is operational withboth V_CCA and V_CCB supplies as low as 0.65 V. The Aport is designed to track V_CCA, which accepts any supply voltage from 0.65 Vto 3.6 V. The B port is designed to track V_CCB, which also accepts anysupply voltage from 0.65 V to 3.6 V.

The DIR pin determines the direction of signal propagation. With the DIR pin configuredHIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B toPort A. The DIR pin is referenced to V_CCA, meaning that its logic-high andlogic-low thresholds track with V_CCA.

This device is fully specified for partial-power-down applications using theI_off current. The I_off protection circuitry ensuresthat no excessive current is drawn from or to an input, output, or combined I/O that is biased to aspecific voltage while the device is powered down.

The V_CC isolation feature ensures that if eitherV_CCA or V_CCB is less than 100 mV, both I/O portsenter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off inany order, providing robust power sequencing performance.

• Up and Down Translation Across 0.65 V to 3.6 V
• Operating Temperature: –40°C to +125°C
• Designed with glitch suppression circuitry to improve power sequencing performance
• Maximum Quiescent Current (I_CCA + I_CCB) of 6 µA (85°C Maximum) and 14 µA (125°C Maximum)
• Up to 500-Mbps Support When Translating from 1.8 to 3.3V
• V_CC Isolation Feature
  • If Either V_CC Input is Below 100 mV, All I/Os Outputs are Disabled and Become High-Impedance
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 8000-V Human Body Model
  • 1000-V Charged-Device Model

All trademarks are the property of their respective owners.