SN74AUP1T157 - Low Power, 1.8/2.5/3.3-V In, 3.3-V CMOS Out, Buffer Multiplexer (Noninverted)

The SN74AUP1T157 is a single 2-input multiplexer that selects data from two data inputs (A and B) under control of a common data select input (C). The state of the common data select input determines the particular register from which the data comes. The output (Y) presents the selected data in the true (non-inverted) form.

AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V V_CC supply. This product also maintains excellent signal integrity (see Figure 2 and Figure 3).

The wide V_CC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (V_T = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

I_off is a feature that allows for powered-down conditions (V_CC = 0 V) and is important in portable and mobile applications. When V_CC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T157 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

Products containing the "SN74AUP1T157" keyword are: SN74AUP1T157DCKR , SN74AUP1T157DCKR

• Single-Supply Voltage Translator
• Output Level Up to Supply V_CC CMOS Level
  • 1.8 V to 3.3 V (at V_CC = 3.3 V)
  • 2.5 V to 3.3 V (at V_CC = 3.3 V)
  • 1.8 V to 2.5 V (at V_CC = 2.5 V)
  • 3.3 V to 2.5 V (at V_CC = 2.5 V
• Schmitt-Trigger Inputs Reject Input Noise and Provide
  Better Output Signal Integrity
• I_off Supports Partial Power Down (V_CC = 0 V)
• Very Low Static Power Consumption:
  0.1 µA
• Very Low Dynamic Power Consumption:
  0.9 µA
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• Pb-Free Packages Available: SC-70 (DCK)
  2 x 2.1 x 0.65 mm (Height 1.1 mm)
• More Gate Options Available at www.ti.com/littlelogic
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model
    (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)