SN74LVT8996 - 3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver

The 'LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPE^TM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPE^TM devices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.

These devices are functionally equivalent to the 'ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to interface to 5-V masters and/or targets.

Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.

Most operations of the ASP are synchronous to the primary test clock (PTCK) input. PTCK is always buffered directly onto the secondary test clock (STCK) output.

Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the assertion of the primary test reset (PTRST\) input or by use of shadow protocol. PTRST\ is always buffered directly onto the secondary test reset (STRST\) output, ensuring that the ASP and its associated secondary TAP can be reset simultaneously.

When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered onto the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while the secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected, STDO is at high impedance, while PTDO is at high impedance, except during acknowledgment of a shadow protocol. Upon disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be synchronously reset to the Test-Logic-Reset state.

In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially at PTDI that matches that at the parallel address inputs (A9-A0), the ASP serially retransmits its address at PTDO as an acknowledgment and then assumes the connected (ON) status, as above. If the received address does not match that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without acknowledgment.

The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving ASPs. The DSA is especially useful when the secondary TAPs of multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the ASP to assume the reset condition, as above. Receipt of the test-synchronization address (TSA) causes the ASP to assume a connect status (MULTICAST) in which PTDO is at high impedance but the connections from PTMS to STMS and PTDI to STDO are maintained to allow simultaneous operation of the secondary TAPs of multiple ASPs. This is useful for multicast TAP-state movement, simultaneous test operation (such as in Run-Test/Idle state), and scanning of common test data into multiple like scan chains. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states.

Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP\) input. This operation is asynchronous to PTCK and is independent of PTRST\ and/or power-up reset. This bypassing feature is especially useful in the board-test environment, since it allows the board-level automated test equipment (ATE) to treat the ASP as a simple transceiver. When the BYP\ input is high, the ASP is free to respond to shadow protocols. Otherwise, when BYP\ is low, shadow protocols are ignored.

Whether the connected status is achieved by use of shadow protocol or by use of BYP\, this status is indicated by a low level at the connect (CON\) output. Likewise, when the secondary TAP is disconnected from the primary TAP, the CON\ output is high.

The SN54LVT8996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT8996 is characterized for operation from -40°C to 85°C.

Products containing the "SN74LVT8996" keyword are: SN74LVT8996DW , SN74LVT8996DW , SN74LVT8996DWR , SN74LVT8996DWR , SN74LVT8996DWRG4 , SN74LVT8996IPWREP , SN74LVT8996IPWREP , SN74LVT8996PW , SN74LVT8996PW , SN74LVT8996PW(LX8996) , SN74LVT8996PWR , SN74LVT8996PWR , SN74LVT8996PWRG4

• Members of the Texas Instruments (TI ^TM) Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
• Extend Scan Access From Board Level to Higher Levels of System Integration
• Promote Reuse of Lower-Level (Chip/Board) Tests in System Environment
• While Powered at 3.3 V, Both the Primary and Secondary TAPs Are Fully 5-V Tolerant for Interfacing to 5-V and/or 3.3-V Masters and Targets
• Switch-Based Architecture Allows Direct Connect of Primary TAP to Secondary TAP
• Primary TAP Is Multidrop for Minimal Use of Backplane Wiring Channels
• Shadow Protocols Can Occur in Any of Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR TAP States to Provide for Board-to-Board Test and Built-In Self-Test
• Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP
• 10-Bit Address Space Provides for up to 1021 User-Specified Board Addresses
• Bypass ( BYP\) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols
• Connect ( CON\) Pin Provides Indication of Primary-to-Secondary Connection
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL) Support Backplane Interface at Primary and High Fanout at Secondary
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Package Options Include Plastic Small-Outline (DW) and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic DIPs (JT)

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