SN74LV4040A - 12-Bit Asynchronous Binary Counter

The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits, counter controls, and frequency-dividing circuits.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Products containing the "SN74LV4040A" keyword are: SN74LV4040AD , SN74LV4040AD , SN74LV4040ADB , SN74LV4040ADBR , SN74LV4040ADBR , SN74LV4040ADBRG4 , SN74LV4040ADG4 , SN74LV4040ADG4 , SN74LV4040ADGVR , SN74LV4040ADGVR , SN74LV4040ADGVRE4 , SN74LV4040ADGVRG4 , SN74LV4040ADR , SN74LV4040ADR , SN74LV4040ADRG4 , SN74LV4040ADRG4 , SN74LV4040ADRG4 (PB) , SN74LV4040AMPWREP , SN74LV4040AMPWREP , SN74LV4040AN

• 2-V to 5.5-V V_CC Operation
• Typical V_OLP (Output Ground Bounce)
     <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
     >2.3 V at V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• High On-Off Output-Voltage Ratio
• Low Crosstalk Between Switches
• Individual Switch Controls
• Extremely Low Input Current
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)