The 165 and LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD\) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD\ high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD\ is high. Data at the parallel inputs are loaded directly into the register while SH/LD\ is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs.
Products containing the "SN54LS165A" keyword are: SN54LS165AJThe SN54165 and SN74165 devices are obsolete and are no longer supplied.
Status | ACTIVE |
SubFamily | Shift register |
Technology Family | LS |
VCC | 5.25 |
Bits | 8 |
Voltage | 5 |
F @ nom voltage | 35 |
ICC @ nom voltage | 30 |
tpd @ Nom Voltage | 25 |
3-state output | No |
Rating | Military |
Operating temperature range | -55 to 125 |
Package Group | CDIP|16 |
Package size: mm2:W x L (PKG) | See datasheet (CDIP) |
Approx. price |