These devices are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
Status | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | AHC |
VCC | 5.5 |
Bits | 8 |
Voltage | 3.3^5 |
F @ nom voltage | 110 |
ICC @ nom voltage | 0.04 |
tpd @ Nom Voltage | 19.5^12.5 |
3-state output | No |
Rating | Military |
Operating temperature range | -55 to 125 |
Package Group | CDIP|20 |
Package size: mm2:W x L (PKG) | See datasheet (CDIP) |
Approx. price |