The SN74LVC1G27 device performs the Boolean function Y = A + B + C or Y = A • B • C in positive logic.
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This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Products containing the "SN74LVC1G27" keyword are: SN74LVC1G27DBVR , SN74LVC1G27DBVR , SN74LVC1G27DBVRE4 , SN74LVC1G27DBVRE4 , SN74LVC1G27DBVRG4 , SN74LVC1G27DCKR , SN74LVC1G27DCKR , SN74LVC1G27DCKR-ND , SN74LVC1G27DCKRE4 , SN74LVC1G27DCKRE4 , SN74LVC1G27DCKRG4 , SN74LVC1G27DCKRG4 , SN74LVC1G27DRYR , SN74LVC1G27DRYR , SN74LVC1G27DSFR , SN74LVC1G27DSFR , SN74LVC1G27YEPR , SN74LVC1G27YZPR , SN74LVC1G27YZPRStatus | ACTIVE |
SubFamily | NOR gate |
Technology Family | LVC |
VCC | 5.5 |
Channels | 1 |
Inputs per channel | 3 |
ICC @ nom voltage | 0.01 |
IOL | 32 |
IOH | -32 |
Input type | Standard CMOS |
Output type | Push-Pull |
Features | Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Ultra High Speed (tpd <5ns) |
Data rate | 100 |
Rating | Catalog |
Operating temperature range | -40 to 125 |
Package Group | DSBGA|6 |
Package size: mm2:W x L (PKG) | See datasheet (DSBGA) |
Approx. price | 0.07 | 1ku |