SN74AUC1G86 - Single 2-Input Exclusive-OR Gate

This single 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC1G86 performs the Boolean function Y = A • B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74AUC1G86" keyword are: SN74AUC1G86DBVR , SN74AUC1G86DBVR , SN74AUC1G86DBVRE4 , SN74AUC1G86DBVRE4 , SN74AUC1G86DBVRG4 , SN74AUC1G86DCKR , SN74AUC1G86DCKR , SN74AUC1G86DCKRE4 , SN74AUC1G86DCKRG4 , SN74AUC1G86YEAR , SN74AUC1G86YEPR , SN74AUC1G86YZAR , SN74AUC1G86YZPR , SN74AUC1G86YZPR

• Available in the Texas Instruments NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• I_off Supports Partial Power-Down-Mode Operation
• Sub-1-V Operable
• Max t_pd of 2.5 ns at 1.8 V
• Low Power Consumption, 10-µA Max I_CC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

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